1. Field of the Invention
The present invention generally relates to data communications, and more particularly, to a method for predicting a total jitter estimation at a predetermined bit error rate for an actual data transmission from a transmitter to a target receiver over an actual backplane link using a software algorithm that (i) creates a mathematical model of the backplane; (ii) generates a waveform simulation of the data transmission across the mathematical model of the backplane; and then (iii) extrapolates the total jitter for the predetermined bit error rate for the data transmission from the waveform simulation.
2. Description of Related Art
In digital data communication systems, bits of information often need to be transmitted from a transmitting location to a receiving location. Typically the transmission occurs across a backplane coupled between the transmitter and the receiver. The transmitter places a sequence of bits through its output ports onto a backplane link. The bits travel across the backplane link to the input ports of the receiver. Current data communication systems are capable of transmitting one Giga-bytes or more of information per second. This figure will continue to grow significantly as semiconductor processing and digital communications systems improve in the future.
With many digital communication systems, the bit error rate or ratio, commonly referred to as “BER,” is used as one specification for measuring the performance of the system. The bit error rate or ratio is the acceptable number of erroneous bits received divided by the total number of bits transmitted. The BER is usually expressed as a coefficient of the power of 10, for example 1 erroneous bit out of 1012 (one trillion). Stated another way, a system having a BER specification of 10−12 requires no more than one erroneous bit for each trillion bits transferred. If the measured number of erroneous bits in a data transmission is one or less, then the system is said to be operating within specification. If the number of erroneous bits is more than one per trillion, then the system is not operating within specification.
Currently the BER is determined in one of two ways. In the first instance, dedicated hardware is provided on the receiver. Logic, typically embedded on the semiconductor chip acting as the receiver, is used to perform the BER calculation. The other alternative is to use dedicated test equipment coupled to the receiver. This hardware is used to calculate the BER and calculate the results during an actual data transmission.
There are a number of problems associated with both solutions. Each require dedicated hardware and logic, either on the receiver chip or off chip, designed for a specific communication system. This hardware and logic is time consuming to design, expensive to make and inflexible. With each new communication system, new hardware and logic will often need to be developed. Lastly, with on-chip solutions, the circuitry used to implement the BER function takes away space on the silicon that could otherwise be used for performing other functions. The BER circuitry is thus overhead that tends to increase the size of the chip, which in turn, may reduce yields. The use of hardware implementations for calculating BER is therefore generally unsatisfactory and less than ideal.
A method is therefore needed for predicting a predetermined bit error rate for an actual data transmission from a transmitter to a target receiver over an actual backplane link using a software algorithm that: (i) creates a mathematical model of the backplane; (ii) generates a waveform simulation of the data transmission over the modeled backplane; and then (iii) extrapolates total jitter for the predetermined bit error rate for the data transmission from the waveform simulation.